Test Name | Status | Notes | Modified |
---|---|---|---|
Board Status | 1 | During initial testing top and bottom failed DRAM test, with top and bottom returning all 0xffffffff. This was probably a problem with the test not the board. Board re-tested with new firmware (V4 v3.16) both top and bottom passed full DRAM test (26/5/08 alex). | 21-07-2008 |
fuses | 1 | 15-06-2008 | |
U31 | 1 | 15-06-2008 | |
U32 | 1 | 15-06-2008 | |
U33 | 1 | 15-06-2008 | |
U34 | 1 | 15-06-2008 | |
U35 | 1 | 15-06-2008 | |
U81 | 1 | 15-06-2008 | |
U82 | 1 | 15-06-2008 | |
I5V_initial | 1 | 15-06-2008 | |
I3V initial | 1 | 15-06-2008 | |
proms load | 1 | 15-06-2008 | |
I5V proms | 1 | 15-06-2008 | |
I3V proms | 1 | 15-06-2008 | |
V4T temp | 1 | 15-06-2008 | |
V4B temp | 1 | 15-06-2008 | |
connectivity | 1 | 15-06-2008 | |
loop data | 1 | 15-06-2008 | |
slink | 1 | 15-06-2008 | |
dram | 1 | Top and bottom failed with all fs.
With new firmware (V4 v3.16) both top and bottom passed full test (26/5/08 alex).
| 15-06-2008 |
nse communication | 1 | 15-06-2008 | |
sram | 15-06-2008 | ||
optical loop | 1 | 15-06-2008 | |
patch panel | 1 | 15-06-2008 | |
qpll lock | 1 | 15-06-2008 | |
ttc connectivity | 1 | 15-06-2008 | |
test fifo | 1 | 15-06-2008 | |
ddr reset | 15-06-2008 | ||
assembly | 1 | 15-06-2008 |