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Status Summary for ROD ID 9

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Test NameStatusNotesModified
Board Status 0 on test bench okay also has 16 MB prom for V2 10 nF capacitor is soldered in VME tested okay; may have once observed flaky LED behavior on bottom V4 LEDs 21 May: very flaky behavior - sometimes events get through on top and bottom, sometimes not; when events don't get through, the data is OKAY from V4 to V2 and in V4 Again, after multiple resets of V4 and setup internal mode, board looked FINE - ran 10,000 events through without a problem ZG2015April29: top has a problem with memory, initializes but something else does not work. Bottom has SRAM error. Since both V4s need exchange and this is the first series board, better to decommission it. 11 June: slink, L1iD, real data through top and bottom okay, ready for pit testing 18 July: Test fifo weirdness read/write errors 13 Aug: Board being used in pit with no problems. 6 May 08: Board shows strange behaviour after loading vchip 2.08. Taken to 104 for further investigation. Could not load vchip v2.08 via xsvf in e-01. Poorly soldered fuse fixed (22/07/08 alex). July 13 -- moved to 104, crystal replaced dec 16, 2014: shipped to UBC for repairs. Feb, 2015: Components replaced (C437,C378,C84_V2,C94_V2,CC5,CC11,C161). 29-04-2015
loop data 0
top half no data, Err: DDR did not initalise correctly
24-11-2013
ddr reset 0
bottom OK, top Err: DDR did not initalise correctly
24-11-2013
fuses 1
06-05-2008
U31
06-05-2008
U32
06-05-2008
U33
06-05-2008
U34
06-05-2008
U35
06-05-2008
U81
06-05-2008
U82
06-05-2008
I5V_initial
06-05-2008
I3V initial
06-05-2008
proms load
06-05-2008
I5V proms
06-05-2008
I3V proms
06-05-2008
V4T temp
06-05-2008
V4B temp
06-05-2008
connectivity
06-05-2008
slink
06-05-2008
dram
06-05-2008
nse communication
06-05-2008
sram
06-05-2008
optical loop
06-05-2008
patch panel 1
06-05-2008
qpll lock 1
06-05-2008
ttc connectivity 1
06-05-2008
test fifo
06-05-2008
assembly 0
see history.
06-05-2008