rods»view/88

Status Summary for ROD ID 88

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Test NameStatusNotesModified
Board Status 1 Passed optics test when small bug fix made to V2, see revision 477, that this board failed this test previously may indicate a V2 chip at the lower end of the speed grade range (03/6/08 alex). While testing CompToggle test with this board as sender saw only 20 channels report at majority, possible testfifo '101' fault requires further investigation (alex 26/06/09). Exhibits fault top and bottom on latch1: 0x3e7fffff noted by Jorge (22/01/10 alex). Board failed in the crate, V4_conf_done led no longer illuminates. Taken out of the crate and placed on the bench for further investigation (04/04/12 alex). ZG06/11/14: Top passes high rate test, bottom sends word 350 equal to previous/next word. ZG2015/March: Everything works since the phase of the V2 and V4 clocks has been adjusted. ZG2015/April: Works well except test FIFO fails at 30kHz event rate, sending to CERN 23-04-2015
nse lookup 1
Ran with ROD internal clock
02-06-2011
fuses 1
03-06-2008
U31 1
03-06-2008
U32 1
03-06-2008
U33 1
03-06-2008
U34 1
03-06-2008
U35 1
03-06-2008
U81 1
03-06-2008
U82 1
03-06-2008
I5V_initial 1
03-06-2008
I3V initial 1
03-06-2008
proms load 1
03-06-2008
I5V proms 1
03-06-2008
I3V proms 1
03-06-2008
V4T temp 1
03-06-2008
V4B temp 1
03-06-2008
connectivity 1
03-06-2008
loop data 1
100k itterations in 100 blocks of 1000; first 100 logs are for top, 2nd 100 are for bottom
03-06-2008
slink 1
Bottom passed, top passed but we also observed the slink busy LED get stuck on and therefore no transmitted data.  New V2 firmware, which was compiled without a cdc and with no timing errors, fixes these problems.
03-06-2008
dram 1
Both top and bottom failed with returned data 0xffffffff.  With V4 v3.07 20/03/08 the bottom passes while the top still fails with 0xffffffff returned. With new mig and ise 10.1 both top and bottom passed.
03-06-2008
nse communication 1
03-06-2008
sram
03-06-2008
optical loop 1
Bottom Passes.  Top Fails intermitently at a delay of 31 and always with other delays. When re-tested top passed but bottom fails with errors on gol0. This appears similar to the fault with board 105 (alex 30/5/08). With minor bug fix to V2, see revision 477, top and bottom now pass optics test (03/6/08 alex).
03-06-2008
patch panel 1
03-06-2008
qpll lock 1
03-06-2008
ttc connectivity 1
03-06-2008
test fifo 1
03-06-2008
ddr reset
03-06-2008
assembly 1
03-06-2008