Test Name | Status | Notes | Modified |
---|---|---|---|
Board Status | 1 | Possible testfifo '101' fault, needs further investigation (alex 26/6/09). | 28-10-2014 |
fuses | 1 | 18-06-2008 | |
U31 | 1 | 18-06-2008 | |
U32 | 1 | 18-06-2008 | |
U33 | 1 | 18-06-2008 | |
U34 | 1 | 18-06-2008 | |
U35 | 1 | 18-06-2008 | |
U81 | 1 | 18-06-2008 | |
U82 | 1 | 18-06-2008 | |
I5V_initial | 1 | 18-06-2008 | |
I3V initial | 1 | 18-06-2008 | |
proms load | 1 | 18-06-2008 | |
I5V proms | 1 | 18-06-2008 | |
I3V proms | 1 | 18-06-2008 | |
V4T temp | 1 | 18-06-2008 | |
V4B temp | 1 | 18-06-2008 | |
connectivity | 1 | 18-06-2008 | |
slink | 1 | 18-06-2008 | |
dram | 1 | Top Passes. Bottom Fails. Reads ffffffff.
With firmware V4 v3.16 bottom passed. | 18-06-2008 |
nse communication | 1 | 18-06-2008 | |
sram | 18-06-2008 | ||
optical loop | 1 | Top Failed with 1016 errors each time. bottom Passed
With New Firmware and delays set to 31, both sides passed | 18-06-2008 |
patch panel | 1 | Rocket IO are always zero even after the IDLE is turned off for both top and bottom. Check next to TTC
Bottom Passes with FSEL set to 100000
Top Passes with FSEL set to 100000 | 18-06-2008 |
qpll lock | 1 | 18-06-2008 | |
ttc connectivity | 1 | 18-06-2008 | |
test fifo | 1 | 18-06-2008 | |
ddr reset | 18-06-2008 | ||
assembly | 1 | 18-06-2008 |