rods»view/8

Status Summary for ROD ID 8

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Test NameStatusNotesModified
Board Status 0 was already loaded with firmware when it came to CERN 16 MB prom instead of 8 MB for V2 tested okay on test bench similar behavior to B05 - LEDs on bottom V4 showed flaky connection also have 10 nF capacitor soldered over R83 21 May: channel 15 on both top and bottom is stuck HIGH - even when masked out data does not seem to be getting through - only a little data very rarely - sometimes no test data gets to bottom and/or top (but not necessarily problem on both halves on same trigger); sometimes data does get through, but even if I mask out the problematic channel only the first trigger gets through the header; no straw data, and no consecutive triggers get data through Requires TWO resets of the V4 before it is functional and then seems to be fine with masked out channels; ran 10,000 events through loop test with compare data for masked channels without a problem 22 May: real data passes on top and bottom of ROD; channel 15 must be a test fifo -> V2 connection problem 11 June: slink, L1iD, real data through top and bottom okay, ready for pit testing 25 June: board returned from CERN shop; passes on-bench connectivity test 101 on test fifo data lines 2(0)-3(31) shows 111 instead of 101- need to mask off bottom two GOLs to get data through from test fifo; normal data works fine Can not seem to write to channel mask register on the top of the board Repowered crate; problem writing to top channel mask register disappeared Real data gets through okay on top and bottom; now test data gets through okay top and bottom?!?! - now board passes all tests? Bizarre - problems were there and then disappeared 28 June: problem with test fifo AND with top channel mask returned!?! Top channel mask problem solved (bad insertion into VME crate) 4 July: pusing on the test fifo quite hard (and in the right place) fixes the problem 5 July: board brought to CERN shop for reheating of test fifo 9 July: board returned from CERN shop; two new channels on vme->v2 chip are open (47 and 33) - pressing on V2 closes connection This problem was not seen before; prevents testing of the test fifo. Complete failure, not longer able to communicate with V4b. No longer functional, given to Philippe for use by the CERN shop in finishing the final RODs. Note that C49, CC3, and CC6 have been removed. Send to Dorigo for temperature profiling (Alex 17/04/13). 17-04-2013
U33
06-05-2008
U34
06-05-2008
U35
06-05-2008
U81
06-05-2008
U82
06-05-2008
I5V_initial
06-05-2008
I3V initial
06-05-2008
proms load
06-05-2008
I5V proms
06-05-2008
I3V proms
06-05-2008
V4T temp
06-05-2008
V4B temp
06-05-2008
connectivity 0
06-05-2008
loop data
06-05-2008
slink
06-05-2008
dram
06-05-2008
nse communication
06-05-2008
sram
06-05-2008
optical loop
06-05-2008
patch panel
06-05-2008
qpll lock
06-05-2008
ttc connectivity
06-05-2008
test fifo 0
V2-testfifo fault.
06-05-2008
ddr reset
06-05-2008
assembly 0
see history.
06-05-2008
fuses 1
06-05-2008
U31
06-05-2008
U32
06-05-2008