rods»view/67

Status Summary for ROD ID 67

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Test NameStatusNotesModified
Board Status 0 dec 16, 2014: shipped to UBC for repairs, DDR init problem on bottom ZG2015April29: bottom DDR does not init 1,2,4,6, bad lines: 15,16,17,37,39,49. Runs bypassing DDR, cannot load compression table. Sending to Dorigo for V4b replacement. 29-04-2015
fuses 1
11-03-2008
U31 1
11-03-2008
U32 1
11-03-2008
U33 1
11-03-2008
U34 1
11-03-2008
U35 1
11-03-2008
U81 1
11-03-2008
U82 1
11-03-2008
I5V_initial 1
11-03-2008
I3V initial 1
11-03-2008
proms load 1
11-03-2008
I5V proms 1
11-03-2008
I3V proms 1
11-03-2008
V4T temp 1
11-03-2008
V4B temp 1
11-03-2008
connectivity 1
11-03-2008
loop data 1
100k itterations in 100 blocks of 1000; first 100 logs are for bottom, 2nd 100 are for top
11-03-2008
slink 1
11-03-2008
dram 1
Top passed 10 100% base address 0 tests, bottom failed with all read data fffffff. Rebooted board and bottom passed. Top and bottom passed 100 100% base assress 0 tests.
11-03-2008
nse communication 1
11-03-2008
sram
11-03-2008
optical loop 1
Top Passed 200 tests, bottom failed 9 from 200 with 254 errors (buffer limit) reported for gol0. With New Firmware and delays set to 31, both sides passed
11-03-2008
patch panel 1
11-03-2008
qpll lock 1
11-03-2008
ttc connectivity 1
11-03-2008
test fifo 1
11-03-2008
ddr reset 1
Bottom passed 1000 (resets) x 10 evts.
11-03-2008
assembly 1
11-03-2008