rods»view/6
Status Summary for ROD ID 6
| Test Name | Status | Notes | Modified |
|---|---|---|---|
| Board Status | 0 | this board was changed by Israel and sent to UPENN; here we had to change the three elements not changed by Israel looked okay on test bench in VME crate, looks okay except upper 2 bits from test fifo to V2 stuck high 21 May - same weird combination of multiple setup steps required; needed to reset V4s and setup internal mode several times (after one reset/setup, state of test fifo on tcl panel changed and needed to refresh to test data!?) Channels 15 and 20 stuck high (TOP AND BOTTOM) going into V2 - maybe a test fifo issue? Passed 10,000 events with bad channels masked out 22 May - With real data, all V2 -> V4 connections are OK on top and bottom - must be problem with test fifo 25 June: board returned from CERN shop; problem connecting to V4/V2/V4 jtag chain Can connect and erase V2 and V4 proms, but when trying to initialize chain, it sees first V4 and then complains about TDI->TDO connection; will go no further C11 on back broken off; same with R2 Wacek replaced these broken components - JTAG connection problem fixed; 10,000 test fifo events in VME pass 31 July 2007: spectacular death in pit; something in VME circuit broke and now freezes crate 10 August 2007 > on bench connectivity test: one connection between V2 (U2s/R23) and V4bottom (U4b/J6) bad (it is BSlink_D<12> line) | 17-10-2008 |
| fuses | 1 | 12-12-2007 | |
| U31 | 12-12-2007 | ||
| U32 | 12-12-2007 | ||
| U33 | 12-12-2007 | ||
| U34 | 12-12-2007 | ||
| U35 | 12-12-2007 | ||
| U81 | 12-12-2007 | ||
| U82 | 12-12-2007 | ||
| I5V_initial | 12-12-2007 | ||
| I3V initial | 12-12-2007 | ||
| proms load | 12-12-2007 | ||
| I5V proms | 12-12-2007 | ||
| I3V proms | 12-12-2007 | ||
| V4T temp | 12-12-2007 | ||
| V4B temp | 12-12-2007 | ||
| connectivity | 12-12-2007 | ||
| loop data | 12-12-2007 | ||
| slink | 12-12-2007 | ||
| dram | 12-12-2007 | ||
| nse communication | 12-12-2007 | ||
| sram | 12-12-2007 | ||
| optical loop | 12-12-2007 | ||
| patch panel | 12-12-2007 | ||
| qpll lock | 12-12-2007 | ||
| ttc connectivity | 12-12-2007 | ||
| test fifo | 0 | Two bits from test fifo to V2 stuck high. | 12-12-2007 |
| ddr reset | 12-12-2007 | ||
| assembly | 0 | see history. | 12-12-2007 |
