Test Name | Status | Notes | Modified |
---|---|---|---|
Board Status | Intermittent DDR initialisation faults making the ROD unstable for data taking in USA15 (31/08/08 alex). Adam and could not reproduce this fault in 104. The ROD has been returned to USA15 and passed a rod_reset_test in e-05. Both this ROD and ROD 50 exhibited the DDR init fault in e-06, could this be a power issue? (16/4/09 alex). Missing components on back side | 22-11-2013 | |
fuses | 1 | 30-05-2008 | |
U31 | 1 | 30-05-2008 | |
U32 | 1 | 30-05-2008 | |
U33 | 1 | 30-05-2008 | |
U34 | 1 | 30-05-2008 | |
U35 | 1 | 30-05-2008 | |
U81 | 1 | 30-05-2008 | |
U82 | 1 | 30-05-2008 | |
I5V_initial | 1 | 30-05-2008 | |
I3V initial | 1 | 30-05-2008 | |
proms load | 1 | 30-05-2008 | |
I5V proms | 1 | 30-05-2008 | |
I3V proms | 1 | 30-05-2008 | |
V4T temp | 1 | 30-05-2008 | |
V4B temp | 1 | 30-05-2008 | |
connectivity | 1 | 30-05-2008 | |
loop data | 1 | 1 dead testfifo to V2 channel<58>(pin B1) resulting in 2 channels not reporting valid preambles. Same fault with boards 21, 41 and 50.Passed 100k top and bottom rod_dual_board_test_log. | 30-05-2008 |
slink | 1 | 30-05-2008 | |
dram | 1 | Top passed, bottom fails with mig stuck in initialisation.Feb 05/08: New DDRManager fixes DRAM (CG) | 30-05-2008 |
nse communication | 1 | 30-05-2008 | |
sram | 30-05-2008 | ||
optical loop | 1 | 30-05-2008 | |
patch panel | 1 | 30-05-2008 | |
qpll lock | 1 | 30-05-2008 | |
ttc connectivity | 1 | 30-05-2008 | |
test fifo | 0 | V2 channel<58>, pin B1 on V2. | 30-05-2008 |
ddr reset | 30-05-2008 | ||
assembly | 1 | 30-05-2008 |