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Status Summary for ROD ID 51

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Test NameStatusNotesModified
Board Status 1 Reset sensitive on J5/J6 ports Feb 05/08: New DDRManager fixes DRAM (CG) dec 16, 2014: shipped to UBC for repairs ZG2015Feb: many dead DDR lines on top. Feb 2015: Components replaced (CC11,C161,R28,C12_Vb). ZG2015April 11: everything works now, not clear what happened before. ZG2015April24: Most likely the fix was that Vincent replaced the missing R28 which is responsible for the top DDR voltage. So it is a good board, but the test FIFO is flaky when NSE is used. 29-04-2015
fuses 1
16-11-2007
U31 1
16-11-2007
U32 1
16-11-2007
U33 1
16-11-2007
U34 1
16-11-2007
U35 1
16-11-2007
U81 1
16-11-2007
U82 1
16-11-2007
I5V_initial 1
16-11-2007
I3V initial 1
16-11-2007
proms load 1
16-11-2007
I5V proms 1
16-11-2007
I3V proms 1
16-11-2007
V4T temp 1
16-11-2007
V4B temp 1
16-11-2007
connectivity 1
16-11-2007
loop data 1
CG, Feb08: Loop data looks good top and bottom
16-11-2007
slink 1
16-11-2007
dram 1
Top passed, bottom fails with mig stuck in initialisation. Feb 05/08: New DDRManager fixes DRAM (CG)
16-11-2007
nse communication 1
16-11-2007
sram
16-11-2007
optical loop 1
16-11-2007
patch panel 1
16-11-2007
qpll lock 1
16-11-2007
ttc connectivity 1
16-11-2007
test fifo 1
16-11-2007
ddr reset
16-11-2007
assembly 1
16-11-2007