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Status Summary for ROD ID 50

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Test NameStatusNotesModified
Board Status 1 Fifo to V2 channels <58> and <57> stuck high: pins B1 and A2, see also boards 21, 41 and 52. Reset once when plugging into J4, J5 after connectivity test; bench test excecuted sucessfully. Passed 100k top and bottom rod_dual_board_test_log in proxy to rod_loop_data_test (28/05/08 alex). Intermittent DDR initialisation faults making the ROD unstable for data taking in USA15 (31/08/08 alex). Moved to SR1 for use in test setup (Late April '09 alex). Moved back to USA15 for slice run, no reported ddr init faults in e-05. 11-05-2010
fuses 1
23-06-2008
U31 1
23-06-2008
U32 1
23-06-2008
U33 1
23-06-2008
U34 1
23-06-2008
U35 1
23-06-2008
U81 1
23-06-2008
U82 1
23-06-2008
I5V_initial 1
23-06-2008
I3V initial 1
23-06-2008
proms load 1
23-06-2008
I5V proms 1
23-06-2008
I3V proms 1
23-06-2008
V4T temp 1
23-06-2008
V4B temp 1
23-06-2008
connectivity 1
23-06-2008
loop data 1
2 dead testfifo to V2 channels <58> and <57> (pins B1 and A2) resulting in 4 channels not reporting valid preambles. See boards 21, 41 and 52. Passed 100k top and bottom rod_dual_board_test_log.
23-06-2008
slink 1
23-06-2008
dram 1
23-06-2008
nse communication 1
23-06-2008
sram
23-06-2008
optical loop 1
23-06-2008
patch panel 1
23-06-2008
qpll lock 1
23-06-2008
ttc connectivity 1
23-06-2008
test fifo 0
V2 channels <58> and <57>, pins B1 and A2
23-06-2008
ddr reset
23-06-2008
assembly 1
23-06-2008