rods»view/5

Status Summary for ROD ID 5

<<Prev | Next>>

Test NameStatusNotesModified
Board Status 0 on the test bench with some power fluctuations that stabilized after awhile - inserted in VME crate and bottom V4 LEDs showed strange behavior (looked unconnected) when ordering of powering on test bench was reversed, V4 chips were reloaded re-soldered fuses - reloading of V4s disappeared still not stable, pin 3 on U33 was not properly soldered; re-soldered; board looks okay on test bench in crate, 16 bad channels between V2 and V4 on the bottom of the board 10 nF capacitor soldered over R83 - stablizes problem of point-probe between R83 and R84 resetting V4s No connection on channel 15 between V4 bottom and V2; however, after pushing on V2 chip, problem disappeared (even when pressure was released) and could run 10,000 events through loopback test with no errors 25 June: board returns from CERN shop; passes on-bench connectivity test 10,000 test fifo events top and bottom through without a problem in VME crate 12 July: two sorts of problems seen after problems in pit: 1) qpll sometimes will not lock in VME crate, creates clock problems and TTC-ROD communication errors, 2) if 3 volt and then 5 volt supply is turned on on the test bench, an extra half amp of current is consumed on the 5 volt supply; this power is consumed in the bottom NSE, which gets quite hot 13 July: loading the V4s with the NSE bit file on the test bench removes the extra half amp consumed by the bottom NSE 19 July: channels 13 and 15 on bottom V2->V4 look open. 2nd April '09: V4 top cannot initialise DDR. (alex) 02-04-2009
fuses 1
12-12-2007
U31
12-12-2007
U32
12-12-2007
U33
12-12-2007
U34
12-12-2007
U35
12-12-2007
U81
12-12-2007
U82
12-12-2007
I5V_initial
12-12-2007
I3V initial
12-12-2007
proms load
12-12-2007
I5V proms
12-12-2007
I3V proms
12-12-2007
V4T temp
12-12-2007
V4B temp
12-12-2007
connectivity
12-12-2007
loop data
12-12-2007
slink
12-12-2007
dram
12-12-2007
nse communication
12-12-2007
sram
12-12-2007
optical loop
12-12-2007
patch panel
12-12-2007
qpll lock
12-12-2007
ttc connectivity
12-12-2007
test fifo
12-12-2007
ddr reset
12-12-2007
assembly 0
pin 3 on U33 was not properly soldered; re-soldered; board looks okay on test bench.
12-12-2007