rods»view/46

Status Summary for ROD ID 46

<<Prev | Next>>

Test NameStatusNotesModified
Board Status 0 ROD sent to York for VME code development (jan '09). ZG2015April29: Bottom DDR does not init, bypassing it the board runs at 10kHz but gets flooded at higher rate. Sending to Dorigo for bottom V4 replacement 29-04-2015
fuses 1
30-10-2007
U31 1
30-10-2007
U32 1
30-10-2007
U33 1
30-10-2007
U34 1
30-10-2007
U35 1
30-10-2007
U81 1
30-10-2007
U82 1
30-10-2007
I5V_initial 1
30-10-2007
I3V initial 1
30-10-2007
proms load 1
30-10-2007
I5V proms 1
30-10-2007
I3V proms 1
30-10-2007
V4T temp 1
30-10-2007
V4B temp 1
30-10-2007
connectivity 1
30-10-2007
loop data 0
Top passed 100k test ok. Bottom fails with the header and error block returned fully but none or only a couple of data words returned, so probably some timing issue in the event builder?
30-10-2007
slink 1
30-10-2007
dram 0
Top passed, bottom fails ~odd word incorrect this maybe the same problem seen on the top of boards 12 and 14.
30-10-2007
nse communication 1
30-10-2007
sram
30-10-2007
optical loop 1
30-10-2007
patch panel 1
30-10-2007
qpll lock 1
30-10-2007
ttc connectivity 1
30-10-2007
test fifo 1
30-10-2007
ddr reset
30-10-2007
assembly 1
30-10-2007