Test Name | Status | Notes | Modified |
---|---|---|---|
Board Status | 1 | Intermitently fails rod_loop_data_test as seen in its failing rod_reset_test; appears to leave off error data sometimes, other times works just fine, and other times no data gets through at all. Top and bottom both pass > 100k events with new firmware (V4 v3.14). | 22-07-2008 |
fuses | 1 | 29-10-2007 | |
U31 | 1 | 29-10-2007 | |
U32 | 1 | 29-10-2007 | |
U33 | 1 | 29-10-2007 | |
U34 | 1 | 29-10-2007 | |
U35 | 1 | 29-10-2007 | |
U81 | 1 | 29-10-2007 | |
U82 | 1 | 29-10-2007 | |
I5V_initial | 1 | 29-10-2007 | |
I3V initial | 1 | 29-10-2007 | |
proms load | 1 | 29-10-2007 | |
I5V proms | 1 | 29-10-2007 | |
I3V proms | 1 | 29-10-2007 | |
V4T temp | 1 | 29-10-2007 | |
V4B temp | 1 | 29-10-2007 | |
connectivity | 1 | 29-10-2007 | |
loop data | 1 | see sttlog39 for failed fifo test 5/14 BM
see history column for details.
Top and bottom both pass > 100k events with new firmware (V4 v3.14). | 29-10-2007 |
slink | 1 | 29-10-2007 | |
dram | 1 | 29-10-2007 | |
nse communication | 1 | 29-10-2007 | |
sram | 29-10-2007 | ||
optical loop | 1 | 29-10-2007 | |
patch panel | 1 | 29-10-2007 | |
qpll lock | 1 | 29-10-2007 | |
ttc connectivity | 1 | 29-10-2007 | |
test fifo | 1 | 29-10-2007 | |
ddr reset | 29-10-2007 | ||
assembly | 1 | 29-10-2007 |