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Status Summary for ROD ID 32

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Test NameStatusNotesModified
Board Status 0 Failed loop data, fifo to V2 ok it looks like a timing issue with signals being latched late/early in the V4 (AM). The same fault as board 25. This board may suffer from the testfifo not being able to drive the 101 on all channels. Is a candidate for testfifo replacement and its operational status could be confirmed using the rod_dual_board_test (27/05/08 alex). Passed 100k top and bottom rod_dual_board_test_log in proxy to rod_loop_data_test (28/05/08 alex). Had ddr init problems in the pit, see ticket 88. Dominick tried moving the ROD to e-05 slot 7 from e-06 slot 9, but the problem persisted. Taken to 104 for further investigation (25/08/09 alex). ZG2015April11: shipped to UBC, runs well bypassing DDR, but bottom DDR fails to init module 6, line 49 looks dead. The test FIFO is flaky, runs only with dual board. 11-04-2015
fuses 1
27-10-2007
U31 1
27-10-2007
U32 1
27-10-2007
U33 1
27-10-2007
U34 1
27-10-2007
U35 1
27-10-2007
U81 1
27-10-2007
U82 1
27-10-2007
I5V_initial 1
27-10-2007
I3V initial 1
27-10-2007
proms load 1
27-10-2007
I5V proms 1
27-10-2007
I3V proms 1
27-10-2007
V4T temp 1
27-10-2007
V4B temp 1
27-10-2007
connectivity 1
27-10-2007
loop data 1
Not all channels repeporting valids and some channels latching early, see history blob for details. Also boards 25 and 49.see sttlog32 for failed fifo test 5/14 BM. Passed 100k top and bottom rod_dual_board_test_log.
27-10-2007
slink 1
27-10-2007
dram 1
27-10-2007
nse communication 1
27-10-2007
sram
27-10-2007
optical loop 1
27-10-2007
patch panel 1
27-10-2007
qpll lock 1
27-10-2007
ttc connectivity 1
27-10-2007
ddr reset
27-10-2007
assembly 1
27-10-2007