Test Name | Status | Notes | Modified |
---|---|---|---|
Board Status | 0 | showed many broken channels between V2 and top V4; board taken to Israel where new V2 was mounted problems between V2 and V4 are fixed but now evidence of (one, two) broken channels between VME chip and V4 top (pins 33 and 2 - was just pin 33 in Israel, back at CERN appears 2 has a problem as well) pushing on top V4 HARD can fix this problem - clears both 2 channels that show bad connection (13 June 2007) board fixed by CERN shop; however, 101 on test fifo data lines 2(0)-3(31) shows 111 instead of 101 - need to mask off bottom two GOLs to get data through from test fifo; normal data works fine June 28: neither pushing on the test fifo nor on the V2 fixes the problem 4 July: pusing on the test fifo quite hard (and in the right place) fixes the problem 5 July: board brought to CERN shop for reheating of test fifo 9 July: some soft short? Consumes too much power on bench on 3.3 V supply and does not work with VME crate 12 July: with Rick's help, seen that power draw results from V2; pushing on V2 increases power consumption; should replace or remove or reball V2?? 15 August 2007: conn_test -> 2 chnls bad betw. V2/V4b; 2 chnls bad betw. V2/V4t; 9 chnls stuck HIGH betw. V2/V4t; 2 chnls bad betw. V4t/V (VME_chip) Consumes too small power on bench. Sent to AppliCAD for temperature profiling. | 24-06-2011 |
fuses | 1 | 12-12-2007 | |
U31 | 12-12-2007 | ||
U32 | 12-12-2007 | ||
U33 | 12-12-2007 | ||
U34 | 12-12-2007 | ||
U35 | 12-12-2007 | ||
U81 | 12-12-2007 | ||
U82 | 12-12-2007 | ||
I5V_initial | 12-12-2007 | ||
I3V initial | 12-12-2007 | ||
proms load | 12-12-2007 | ||
I5V proms | 12-12-2007 | ||
I3V proms | 12-12-2007 | ||
V4T temp | 12-12-2007 | ||
V4B temp | 12-12-2007 | ||
connectivity | 12-12-2007 | ||
loop data | 12-12-2007 | ||
slink | 12-12-2007 | ||
dram | 12-12-2007 | ||
nse communication | 12-12-2007 | ||
sram | 12-12-2007 | ||
optical loop | 12-12-2007 | ||
patch panel | 12-12-2007 | ||
qpll lock | 12-12-2007 | ||
ttc connectivity | 12-12-2007 | ||
test fifo | 0 | See history | 12-12-2007 |
ddr reset | 12-12-2007 | ||
assembly | 0 | see history. | 12-12-2007 |