rods»view/25
Status Summary for ROD ID 25
| Test Name | Status | Notes | Modified |
|---|---|---|---|
| Board Status | 1 | Failed loop data, fifo to V2 ok it looks like a timing issue with signals being latched late/early in the V4 (AM). This is an intermittent fault and is repeated on board 32. | 22-07-2008 |
| fuses | 1 | 26-10-2007 | |
| U31 | 1 | 26-10-2007 | |
| U32 | 1 | 26-10-2007 | |
| U33 | 1 | 26-10-2007 | |
| U34 | 1 | 26-10-2007 | |
| U35 | 1 | 26-10-2007 | |
| U81 | 1 | 26-10-2007 | |
| U82 | 1 | 26-10-2007 | |
| I5V_initial | 1 | 26-10-2007 | |
| I3V initial | 1 | 26-10-2007 | |
| proms load | 1 | 26-10-2007 | |
| I5V proms | 1 | 26-10-2007 | |
| I3V proms | 1 | 26-10-2007 | |
| V4T temp | 1 | 26-10-2007 | |
| V4B temp | 1 | 26-10-2007 | |
| connectivity | 1 | 26-10-2007 | |
| loop data | 1 | Not all channels repeporting valids and some channels latching early, see history blob for details. Also boards 32 and 49.
Looks OK on May 11/08 -BM | 26-10-2007 |
| slink | 1 | 26-10-2007 | |
| dram | 1 | 26-10-2007 | |
| nse communication | 1 | 26-10-2007 | |
| sram | 26-10-2007 | ||
| optical loop | 1 | 26-10-2007 | |
| patch panel | 1 | 26-10-2007 | |
| qpll lock | 1 | 26-10-2007 | |
| ttc connectivity | 1 | 26-10-2007 | |
| test fifo | 1 | 26-10-2007 | |
| ddr reset | 26-10-2007 | ||
| assembly | 1 | 26-10-2007 |
