Test Name | Status | Notes | Modified |
---|---|---|---|
Board Status | 1 | 28-07-2008 | |
fuses | 1 | 25-10-2007 | |
U31 | 1 | 25-10-2007 | |
U32 | 1 | 25-10-2007 | |
U33 | 1 | 25-10-2007 | |
U34 | 1 | 25-10-2007 | |
U35 | 1 | 25-10-2007 | |
U81 | 1 | 25-10-2007 | |
U82 | 1 | 25-10-2007 | |
I5V_initial | 1 | 25-10-2007 | |
I3V initial | 1 | 25-10-2007 | |
proms load | 1 | 25-10-2007 | |
I5V proms | 1 | 25-10-2007 | |
I3V proms | 1 | 25-10-2007 | |
V4T temp | 1 | 25-10-2007 | |
V4B temp | 1 | 25-10-2007 | |
connectivity | 1 | 25-10-2007 | |
loop data | 1 | 1 dead testfifo to V2 channel<57> (pin A2) resulting in 2 channels not reporting valid preambles. Same fault with boards 41, 50 and 52.Passed 100k top and bottom rod_dual_board_test_log. | 25-10-2007 |
slink | 1 | 25-10-2007 | |
dram | 1 | 25-10-2007 | |
nse communication | 1 | 25-10-2007 | |
sram | 25-10-2007 | ||
optical loop | 1 | 25-10-2007 | |
patch panel | 1 | 25-10-2007 | |
qpll lock | 1 | 25-10-2007 | |
ttc connectivity | 1 | 25-10-2007 | |
test fifo | 0 | V2 channel<57>, pin A2 on V2. | 25-10-2007 |
ddr reset | 25-10-2007 | ||
assembly | 1 | 25-10-2007 |