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Status Summary for ROD ID 2

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Test NameStatusNotesModified
Board Status 0 tested fine initially and was in pit; was found to have problem with L1ID on top half of board to be checked more thoroughly in 104 - misc to V4 soldering problem? Turned out to be bad link between V2 and V4 top on slink connection pin 13 June: Board brought to CERN shop for reheating of V2 Connection between V2 and V4 slink problem solved 29 June: problem returned. Exact same line (74) is open again after being in pit for two weeks. 5 July: board brought to CERN shop for reheating (take 2) of V2 chip to see if it can fix the problem 9 July: board might be okay; connection looks fixed but am I losing one or two events from 10000 with the slink? 19 July: problem on channel returned 13 Aug: verified (bcl + WO) that line 74 of V2-V4t is still open (V2 pin A25). Pushing on V2 will bring the line back temporarily. Recommend board for V2 replacement at CERN shop. Board is operational in USA15 so is considered to have passed all tests, this might need to be verified at some point (alex 8/5/08). Still some concerns that this board is really fully operational, see history above. dec 16, 2014: sent to UBC for repair. Feb, 2015: Components replaced (CC11,C102_Vb,C25_Nb, C13_Nb,C161,C8R,C9R,C16_Vt,C418,C272,R1). 29-04-2015
fuses 1
08-05-2008
U31
08-05-2008
U32
08-05-2008
U33
08-05-2008
U34
08-05-2008
U35
08-05-2008
U81
08-05-2008
U82
08-05-2008
I5V_initial
08-05-2008
I3V initial
08-05-2008
proms load
08-05-2008
I5V proms
08-05-2008
I3V proms
08-05-2008
V4T temp
08-05-2008
V4B temp
08-05-2008
connectivity 0
08-05-2008
loop data 1
08-05-2008
slink 1
08-05-2008
dram 1
08-05-2008
nse communication 1
08-05-2008
sram
08-05-2008
optical loop 1
08-05-2008
patch panel 1
08-05-2008
qpll lock 1
08-05-2008
ttc connectivity 1
08-05-2008
test fifo
08-05-2008
ddr reset
08-05-2008
assembly
08-05-2008