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Status Summary for ROD ID 14

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Test NameStatusNotesModified
Board Status 1 Sep 07: Top suffers from DDR-V4 calibration problems. June 27: on-bench power and connectivity test looks good in crate! 100,000 test fifo events and 10,000 real events ./ttc_rod for 1000, 10000 resets and triggers 100 slink events 100 seconds rocketio loopback. With V4 v3.16 top and bottom now pass loop data test (28/5/08 alex). 23-07-2008
fuses 1
28-05-2008
U31
28-05-2008
U32
28-05-2008
U33
28-05-2008
U34
28-05-2008
U35
28-05-2008
U81
28-05-2008
U82
28-05-2008
I5V_initial
28-05-2008
I3V initial
28-05-2008
proms load
28-05-2008
I5V proms
28-05-2008
I3V proms
28-05-2008
V4T temp
28-05-2008
V4B temp
28-05-2008
connectivity 1
28-05-2008
loop data 1
With V4 v3.16 Top and bottom both passed 100k evts. Top also passed a multiple resest test with 1000 resets each followed by 100 evts. Previously the bit shifted date error would always be present after between 20-30 resets (28/5/08 alex).
28-05-2008
slink 1
28-05-2008
dram 1
28-05-2008
nse communication 1
28-05-2008
sram
28-05-2008
optical loop 1
28-05-2008
patch panel 1
28-05-2008
qpll lock 1
28-05-2008
ttc connectivity 1
28-05-2008
test fifo 1
28-05-2008
ddr reset
28-05-2008
assembly
28-05-2008