rods»view/123

Status Summary for ROD ID 123

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Test NameStatusNotesModified
Board Status 1 unable to write to id_prom, when executing
rod_write_id_prom 7 123 results in:
This board has the ID serial prom number: 32891
further tests failed as well. The sequence: simple_setup.sh, rod_send_self_l1a, and rod_test_dma, produce segmentation fault
June 17/2011:
After further checks with ChipScope, it was determined that the line vme_D15 was faulty, it seems to be stuck high.
June 24/2011:
One of the unused pins from the VME driver was used to bridge the faulty line D15 to the VChip (lift pin 23 from chip U4, and bridge it to pin 28 of U6) A customized VChip firmware was created to reroute the signals. After this fix, direct writing/reading into/from a given VME address using D15 seems to work. The prom_id chip was set to 123. Further testing failed. When next to a TTC the card is not reaching QPLL lock.
June 29/2011:
Board returned from the e-shop where the QPLL crystal was replaced. The board now locks to the TTC. While next to the TTC the board passed a loop_data test but still failed the sram test. I moved the ROD to a standalone slot and added slinks. The ROD now passes the sram test? I have moved the board back next to the TTC and kept the slink cards. The board still passes the sram test?(Alex)
CG: VME line moved from D15 (U4 pin 23) to IRQ6 (U6 Pin 48), not what is listed above ZG2015April11: was shipped to UBC after failing tests in 104 but it works well, must have done wrong tests in 104. ZG2015April23: probably loaded compare file instead of input file into the test FIFO, works well, sending to CERN. April 2015: Components Replaced (C378).
29-04-2015
optical loop 1
18-05-2012
dram 1
16-05-2012
ddr reset 1
But need to run longer
16-05-2012
test fifo 1
16-05-2012
ttc connectivity 1
moderate level of test. Maybe run longer ...
16-05-2012
nse lookup 1
45k passed top and bottom
14-05-2012
slink 1
All ok
14-05-2012
qpll lock 0
CG: It was locking fine after xtal replacement. After recent power cycle, not locking. However, all high-speed tests on board are working. Perhaps lock line is simply intermittent? Locks to TTC fine, though.
11-05-2012
assembly 1
See notes about VME rerouting. No other problems evident so far.
11-05-2012
patch panel 1
11-05-2012
sram 1
Ok after VME fix
11-05-2012
loop data 1
10k events top/bottom. Will do more later
11-05-2012
nse communication 1
27-06-2011
V4T temp 1
16-05-2011
V4B temp 1
16-05-2011
V4T temp 1
16-05-2011
I3V proms 1
16-05-2011
I5V proms 1
16-05-2011
connectivity 1
16-05-2011
proms load 1
16-05-2011
U82 1
16-05-2011
U81 1
16-05-2011
U35 1
16-05-2011
U34 1
16-05-2011
U33 1
16-05-2011
U32 1
16-05-2011
U31 1
16-05-2011
I3V initial 1
16-05-2011
I5V_initial 1
16-05-2011
fuses 1
13-05-2011