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Status Summary for ROD ID 120

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Test NameStatusNotesModified
Board Status 0 Sent to Dorigo for NSE x-ray. Single dma read back failed on bottom. It looks like the ddr init is failing. April 2015: Components replaced (C436). ZG2015April29: bottom DDR fails line 39 and comp 4,5. Bypassing memory doesn't work, no event accept from V2 to V4?. Needs replacing U4b. 29-04-2015
nse communication 1
Good after sending to Dorigo
24-11-2013
optical loop 1
13-06-2011
nse lookup 0
top passed, bottom failed
13-06-2011
sram 0
top passed, bottom failed
13-06-2011
patch panel 1
13-06-2011
ddr reset 1
13-06-2011
test fifo 1
13-06-2011
slink 0
top passed, bottom failed
13-06-2011
dram 0
top passed, bottom failed
13-06-2011
ttc connectivity 1
13-06-2011
qpll lock 1
fails to lock on internal mode
13-06-2011
nse communication 0
top passed, bottom failed
13-06-2011
loop data 0
13-06-2011
assembly 1
26-05-2011
V4B temp 1
13-05-2011
V4T temp 1
13-05-2011
I3V proms 1
13-05-2011
I5V proms 1
13-05-2011
connectivity 1
13-05-2011
proms load 1
13-05-2011
U82 1
13-05-2011
U81 1
13-05-2011
U35 1
13-05-2011
U34 1
13-05-2011
U33 1
13-05-2011
U32 1
13-05-2011
U31 1
13-05-2011
I3V initial 1
13-05-2011
I5V_initial 1
13-05-2011
fuses 1
13-05-2011