rods»view/116

Status Summary for ROD ID 116

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Test NameStatusNotesModified
Board Status B Start of testing of new production run. ZG7/11/14: no ROD busies from both top and bottom, suspecting U2 chip is blown. Feb, 2015: Component replaced (C442). 29-04-2015
nse lookup 1
Ran with TTC clock
02-06-2011
ddr reset 1
100 reboots with 1000 resets took ~75 minutes. No QPLL lock boot errors. No top boot DDR errors. No bottom boot DDR errors. No top reset DDR errors. No bottom reset DDR errors. No top boot NSE errors. No bottom boot NSE errors. No top reset NSE errors. No bottom reset NSE errors.
10-03-2011
assembly 1
One issue is the alignment of the backplane connector. The TTC connector (J3) appears misaligned with the other two when visually inspected. Will not insert into crate without extra manual guidance. The middle connector is particularly out of alignment when inserting and board damage is likely if care is not taken (Alex).
10-03-2011
dram 1
Only V4 firmware pre v3.17 supports this test. Used archive/V4270508.xsvf (v3.16). Use this version for future tests.
10-03-2011
optical loop 1
Current release V2 firmware (V2160709.xsvf) has a bug preventing optical loop test from working. Reverted to V2 version archive/V2test03608.xsvf (v3.10). This is the version including the bug fix in svn revision 477. With this version of the V2 the optical test initially failed on the bottom. The first failure was only on observed on gol:2. The transmitters from gol:2 and gol:3 were swapped and no errors were observed. However with the driver from gol:2 driving gol:0 errors were observed on gol:1 and gol:0 during the same test. The test was run again with the transmitter from gol:2 driving in turn each receiver with no errors observed. The transmitter/receiver pairings were then returned to their default configuration and tested for twelve hours without any failure. The board has been given a pass status for this test with the suspicion that the initial failures were down to an obstruction internal to the transceiver (Alex).
10-03-2011
qpll lock 1
09-03-2011
loop data 1
Failed one test with failure in word 9, this is the l1id. I think this is a configuration issue dues to running the TTC test directly before and hence the rod is not generating it's internal l1id as expected. Need to check how we reconfigure from TTC to loop data test as something is missing. Passed 100,000 top and bottom after fresh configuration to internal data mode.
09-03-2011
test fifo 1
08-03-2011
patch panel 1
08-03-2011
sram 1
08-03-2011
nse communication 1
08-03-2011
slink 1
08-03-2011
connectivity 1
08-03-2011
V4B temp 1
08-03-2011
V4T temp 1
08-03-2011
I3V proms 1
08-03-2011
I5V proms 1
08-03-2011
U82 1
08-03-2011
U81 1
08-03-2011
U35 1
08-03-2011
U34 1
08-03-2011
U33 1
08-03-2011
U32 1
08-03-2011
U31 1
08-03-2011
proms load 1
08-03-2011
I3V initial 1
08-03-2011
I5V_initial 1
08-03-2011
fuses 1
Installed
08-03-2011