Test Name | Status | Notes | Modified |
---|---|---|---|
Board Status | B | DDR init problem reported on top dec 16, 2014: shipped to UBC for repairs. Feb, 2015: Components replaced (CC11). ZG2015April29: bottom DDR fails init 3, flaky line 31; top DDR fails init 6, flaky 48. Works bypassing DDR. Sending to Dorigo to replace U4t and U4b. | 29-04-2015 |
fuses | 1 | 13-06-2008 | |
U31 | 1 | 13-06-2008 | |
U32 | 1 | 13-06-2008 | |
U33 | 1 | 13-06-2008 | |
U34 | 1 | 13-06-2008 | |
U35 | 1 | 13-06-2008 | |
U81 | 1 | 13-06-2008 | |
U82 | 1 | 13-06-2008 | |
I5V_initial | 1 | 13-06-2008 | |
I3V initial | 1 | 13-06-2008 | |
proms load | 1 | 13-06-2008 | |
I5V proms | 1 | 13-06-2008 | |
I3V proms | 1 | 13-06-2008 | |
V4T temp | 1 | 13-06-2008 | |
V4B temp | 1 | 13-06-2008 | |
connectivity | 1 | 13-06-2008 | |
loop data | 1 | 13-06-2008 | |
slink | 1 | 13-06-2008 | |
dram | 1 | 13-06-2008 | |
nse communication | 1 | 13-06-2008 | |
sram | 13-06-2008 | ||
optical loop | 1 | 13-06-2008 | |
patch panel | 1 | 13-06-2008 | |
qpll lock | 1 | 13-06-2008 | |
ttc connectivity | 1 | 13-06-2008 | |
test fifo | 1 | 13-06-2008 | |
ddr reset | 13-06-2008 | ||
assembly | 1 | 13-06-2008 |