Test Name | Status | Notes | Modified |
---|---|---|---|
Board Status | 1 | During original testing board failed DRAM test top and bottom: ffffffff returned. With V4 v3.16 top passed full DRAM test, bottom still failed (27/05/08 alex). The bottom passed the DRAM test with V4 v3.16 27/5/2008, this is a version of the V4 with the DDR_FSM registers included and hence a slightly different V4 routing (27/05/08 alex). | 01-08-2008 |
fuses | 1 | 13-06-2008 | |
U31 | 1 | 13-06-2008 | |
U32 | 1 | 13-06-2008 | |
U33 | 1 | 13-06-2008 | |
U34 | 1 | 13-06-2008 | |
U35 | 1 | 13-06-2008 | |
U81 | 1 | 13-06-2008 | |
U82 | 1 | 13-06-2008 | |
I5V_initial | 1 | 13-06-2008 | |
I3V initial | 1 | 13-06-2008 | |
proms load | 1 | 13-06-2008 | |
I5V proms | 1 | 13-06-2008 | |
I3V proms | 1 | 13-06-2008 | |
V4T temp | 1 | 13-06-2008 | |
V4B temp | 1 | 13-06-2008 | |
connectivity | 1 | 13-06-2008 | |
loop data | 1 | 13-06-2008 | |
slink | 1 | 13-06-2008 | |
nse communication | 1 | 13-06-2008 | |
sram | 13-06-2008 | ||
optical loop | 1 | 13-06-2008 | |
patch panel | 1 | 13-06-2008 | |
qpll lock | 1 | 13-06-2008 | |
ttc connectivity | 1 | 13-06-2008 | |
test fifo | 1 | 13-06-2008 | |
ddr reset | 13-06-2008 | ||
assembly | 1 | 13-06-2008 |