ROD Firmware Summary

Firmware for vme

version date changelog action
2.11 2009-04-21 Correct version number implemented. spyfifo overflow debug register removed. Reset replaced by AnyReset signal in process which controls vme access LED. edit
ff.ff 2009-01-20 A test version of the vme firmware that was used for early 2009 running of the TRT, replaced by version 2.11 before the TRT slice run starting 27/4/09. Debug register, added spyfifo overflow flag. Cosmetic change to VmeIntfce.vhd, current replaced by State and nexts replaced by NextState. This code now matchs the rest of the rod vhdl state names. spyfifo.xco regenerated. edit
ff.ff 2008-11-05 A test version of the vme firmware that was used for the ID combined run in late november/early december 2008. Increase to spy fifo vme address space. This allows large vme block transfers of spy data to take place, previously the vme address space was limiting the use of continuous block transfers. Bug fix to the request of spy data from the V4, previously this could happen one clk tick early and result in the merger of data in particular 0xee1234ee appearing in the data. Debug register added to count number of spy data words received by the vme spy fifo: SPY_EVT_CNT_ADDR_B = X"13" SPY_EVT_CNT_ADDR_T = X"14" edit
2.10 2008-06-19 Fixed upper two bits in VME addressing to be 0 for our custom TRT vme mapping. edit

Firmware for misc

version date changelog action
3.07 2009-08-31 Updates internal auto l1a to run with 18 evts in testfifo. edit
3.02 2008-08-27 Include QPLL loss count in misc debug registers. Status of QPLL Lock count register, u_int32 qpllLockCntCR; address 0x180. Reset of counts, u_int32 qpllLockCntSR; address 0x184. edit

Firmware for V2

version date changelog action
3.20 2009-07-16 Copy of branches/V2Slinkfifo to trunk/V2. This is V2 version 3.20 containing a fifo to receive the slink data from the V4. This version is for use with V4 version 3.20 and onwards. edit
3.12 2008-10-21 Fixed bug in rocket_io.vhd: The bug resulted in a misalignment of the pointer to the rocketio derandomiser fifo if the IDLE to DATA transition happened at the same time as a the pointer alignment code performed a word skip operation in the derandomiser fifo. Fixed remaining error with the GOL delay scans. edit
3.11 2008-08-13 Bottom rocketIO lock led order (fixed) reversed. Update to allow event by event channel masking based on channels that do not report '101'. Controled from c-code by rod_set_preamble_mask(rod_half half, u_int32 preMask). Bug fix in RocketIOManager.vhd which now assigns iTestDataIn into compare_fifo correctly for loopback test code. Compare fifo regenerated with synchronous re/wr clk. Fixed RocketIOManager to transmit both the top and bottom 16 bits of data (was just sending bottom twice). Change routing of test data in RocketIOManager.vhd: Data using the tx out used to also be sent via bypass to the V4. Now it only bypasses only if set. edit
3.10 2008-04-18 edit

Firmware for V4

version date changelog action
3.26 2010-04-26 Stop raw reads of the DDR until previous event has been fully returned from the MIG. Fixes high rate high occupancy problem. edit
3.1a 0000-00-00 Changes to clock distribution across the chip: to correct NSE/sram lookup timing, seperate clock for NSE/sram added. Clock chain in ClkGen reordered, 80MHz clk now sourced from DCM80 not 2x from DCM40. Added partial reset through AnyReset signal, partialreset and PRst removed. DDR FSM history fifo added. BCid mismatch fixed. Data to/from NSE/sram now latched to/from the V4 for safety. LED IDLE rotation code fixed. Replaced InputDataSM receive fifo with SRL16 shift registers to save fifo resoures. Increased depth of fifos either side of spy DDR I/O to prevent fifo overflow. Updated all fifos to version 4.4. Update Block Memory Generator to version 2.8. Reduced combinatorial logic in DDRManager to improve timing and routing of DDR control signals. Tightened timing constraints on 160MHz clock to 50% high 5.9ns. Replaced internal 120MHz DDRManager/MIG clock with 160MHz clock. Updated to MIG 2.3, mig 2.3 has improved timing characteristics. Added header signals into DDR, see header_reroute branch. Header signals now have same path as straw data. edit